The UVE project creates software that automatically generates verification testbenches (TB) written in SystemVerilog (SV) integrating the UVM methodology.

UVE makes the development of verification environments rapid and simple. The generated TB performs random actions on the DUV. It provides a graphical user interface, a code generator, compilation scripts and a library of verification IPs (VIP). One of the main innovations of UVE is a list of TODOs in the TB code to help finalizing the TB. This is especially useful for developers not familiar with SV and/or UVE, but also experienced developers profit from that task list.

The graphical interface lets the user observe and navigate the structure of the generated testbench. Simulation is launched directly from the tool.